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3.75 kv, 6-channel digital isolator for spi preliminary technical data adum3150 rev. pra document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2014 analog devices, inc. all rights reserved. technical support www.analog.com features supports up to 17 mhz spi clock speed supports up to 40 mhz spi clock speed in delay clock mode 4 high speed, low propagation delay, spi signal isolation channels two 250 kbps data channels delayed compensation clock line 20-lead ssop package with 5 mm creepage high temperature operation: 125c high common-mode transient immunity: >25 kv/s safety and regulatory approvals ul recognition per ul 1577 (pending) 3750 v rms for 1 minute csa component acceptance notice 5a (pending) vde certificate of conformity (pending) din v vde v 0884-10 (vde v 0884-10):2006-12 v iorm = 560 v peak applications industrial programmable logic controllers (plc) sensor isolation functional block diagram encode clk delay control block decode decode encode encode decode encode decode v dd1 gnd 1 mclk mo mi mss v ia v ob v dd2 gnd 2 sclk si so sss v oa v ib 1 2 3 4 5 6 7 8 20 19 18 17 16 15 14 13 dclk gnd 1 nic gnd 2 9 10 12 11 adum3150 12367-001 control block figure 1. general description the adum3150 1 is a six-channel spisolator? digital isolator optimized for isolated serial peripheral interfaces (spi). based on the analog devices, inc., i coupler? chip-scale transformer technology, the low propagation delay and jitter in the clk, mo/si, mi/so, and ss channels support spi clock rates of up to 17 mhz. the adum3150 isolator also provides two additional independent low data rate isolation channels, one channel in each direction. data in the slow channels is sampled and serialized for a 250 kbps data rate with 2.5 s of jitter. the adum3150 also supports a delay clock output on the master side of the device. this output can be used with an additional spi port on the master to support 40 mhz clock performance. see the delay clock section for more information. table 1. related products product description adum3151 3.75 kv, multichannel spi isolator adum3152 3.75 kv, multichannel spi isolator adum3153 3.75 kv, multichannel spi isolator adum3154 3.75 kv, multiple slave select spi isolator 1 protected by u.s. patents 5,952,849; 6,873,065; 6, 903,578; and 7,075,329. other patents are pending.
adum3150 preliminary technical data rev. pra | page 2 of 21 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? specifications ..................................................................................... 3 ? electrical characteristics5 v operation................................ 3 ? electrical characteristics3.3 v operation ............................ 5 ? electrical characteristicsmixed 5 v/3.3 v operation ........ 7 ? electrical characteristicsmixed 3.3 v/5 v operation ........ 9 ? package characteristics ............................................................. 11 ? regulatory information ............................................................. 11 ? insulation and safety-related specifications .......................... 11 ? din v vde v 0884-10 (vde v 0884-10):2006-12 insulation characteristics ............................................................................ 12 ? recommended operating conditions .................................... 12 ? absolute maximum ratings ......................................................... 13 ? esd caution................................................................................ 13 ? pin configuration and function descriptions ........................... 14 ? typical performance characteristics ........................................... 15 ? applications information .............................................................. 16 ? introduction ................................................................................ 16 ? printed circuit board (pcb) layout ....................................... 17 ? propagation delay related parameters ................................... 18 ? dc correctness and magnetic field immunity ..................... 18 ? power consumption .................................................................. 19 ? insulation lifetime ..................................................................... 19 ? outline dimensions ....................................................................... 21 ? ordering guide .......................................................................... 21 ?
preliminary technical data adum3150 rev. pra | page 3 of 21 specifications electrical characteristics5 v operation all typical specifications are at t a = 25c and v dd1 = v dd2 = 5 v. minimum and maximum specifications apply over the entire recommended operation range: 4.5 v v dd1 5.5 v, 4.5 v v dd2 5.5 v, and ?40c t a +125c, unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels, unless otherwise noted. table 2. switching specifications parameter symbol a grade b grade unit test conditions/comments min typ max min typ max mclk, mo, so spi clock rate spi mclk 40 17 mhz data rate fast (mo, so) dr fast 40 40 mbps within pwd limit propagation delay t phl , t plh 25 12 14 ns 50% input to 50% output pulse width pw 12.5 12.5 ns within pwd limit pulse width distortion pwd 3 2 ns |t plh ? t phl | codirectional channel matching 1 t pskcd 3 2 ns jitter, high speed j hs 1 1 ns mss data rate fast dr fast 40 40 mbps within pwd limit propagation delay t phl , t plh 21 25 21 25 ns 50% input to 50% output pulse width pw 12.5 12.5 ns within pwd limit pulse width distortion pwd 3 3 ns |t plh ? t phl | setup time 2 mss setup 1.5 10 ns jitter, high speed j hs 1 1 ns dclk data rate 40 40 mhz propagation delay t phl , t plh 33 33 ns t pmclk + t pso + 3 ns pulse width distortion pwd 2 2 ns |t plh ? t phl | pulse width pw 12 12 ns within pwd limit jitter j dclk 1 1 ns v ia , v ib data rate slow dr slow 250 250 kbps within pwd limit propagation delay t phl , t plh 0.1 2.6 0.1 2.6 s 50% input to 50% output pulse width pw 4 4 s within pwd limit jitter, low speed j ls 2.5 2.5 s v ix 3 minimum input skew 4 t vix skew 10 10 ns 1 codirectional channel matching is the absolute value of the di fference in propagation delays between any two channels with inp uts on the same side of the isolation barrier. 2 the mss signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the b grade. to guar antee that mss reaches the output ahead of another fast signal, set up mss prior to the competing signal by different times depending on speed grade. 3 v ix = v ia or v ib . 4 an internal asynchronous clock not available to users samples the low speed signals. if edge sequence in codirectional channel s is critical to the end application, the leading pulse must be at least 1 t vix skew time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.
adum3150 preliminary technical data rev. pra | page 4 of 21 table 3. for all grades 1, 2, 3 parameter symbol min typ max unit test conditions/comments supply current 1 mhz, a grade and b grade i dd1 4.0 5.0 ma c l = 15 pf, dr fast = 1 mhz, dr slow = 0 mhz i dd2 6.0 10.0 ma c l = 15 pf, dr fast = 1 mhz, dr slow = 0 mhz 17 mhz, b grade i dd1 14.0 16.5 ma c l = 15 pf, dr fast = 17 mhz, dr slow = 0 mhz i dd2 13.3 16.0 ma c l = 15 pf, dr fast = 17 mhz, dr slow = 0 mhz dc specifications mckl, mss , mo, so, v ia , v ib logic high input threshold v ih 0.7v ddx v logic low input threshold v il 0.3v ddx v input hysteresis v ihyst 500 mv input current per channel i i ?1 +0.01 +1 a 0 v v input v ddx sclk, sss , mi,si, v oa , v ob , dclk logic high output voltages v oh v ddx ? 0.1 5.0 v i output = ?20 a, v input = v ih v ddx ? 0.4 4.8 v i output = ?4 ma, v input = v ih logic low output voltages v ol 0.0 0.1 v i output = 20 a, v input = v il 0.2 0.4 v i output = 4 ma, v input = v il v dd1 , v dd2 undervoltage lockout uvlo 2.6 v supply current for high speed channel dynamic input supply current i ddi(d) 0.09 ma/mbps dynamic output supply current i ddo(d) 0.02 ma/mbps supply current for all low speed channels quiescent input supply current i ddi(q) 4.0 ma quiescent output supply current i ddo(q) 6.4 ma ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common-mode transient immunity 4 |cm| 25 35 kv/s v input = v ddx , v cm = 1000 v transient magnitude = 800 v 1 v ddx = v dd1 or v dd2 . 2 v input is the input voltage of any of the mclk, mss , mo, so, v ia , or v ib pins. 3 i output is the output current of any of the sclk, dclk, sss , mi, si, v oa , or v ob pins. 4 |cm| is the maximum common-mode voltage sl ew rate that can be sustained while maintaining output voltages within the v oh and v ol limits. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
preliminary technical data adum3150 rev. pra | page 5 of 21 electrical characteristics3.3 v operation all typical specifications are at t a = 25c and v dd1 = v dd2 = 3.3 v. minimum and maximum specifications apply over the entire recommended operation range: 3.0 v v dd1 3.6 v, 3.0 v v dd2 3.6 v, and ?40c t a +125c, unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels, unless otherwise noted. table 4. switching specifications parameter symbol a grade b grade unit test conditions/comments min typ max min typ max mclk, mo, so spi clock rate spi mclk 40 12.5 mhz data rate fast (mo, so) dr fast 40 40 mbps within pwd limit propagation delay t phl , t plh 30 20 ns 50% input to 50% output pulse width pw 12.5 12.5 ns within pwd limit pulse width distortion pwd 3 3 ns |t plh ? t phl | codirectional channel matching 1 t pskcd 4 2 ns jitter, high speed j hs 1 1 ns mss data rate fast dr fast 40 40 mbps within pwd limit propagation delay t phl , t plh 30 30 ns 50% input to 50% output pulse width pw 12.5 12.5 ns within pwd limit pulse width distortion pwd 3 3 ns |t plh ? t phl | setup time 2 mss setup 1.5 10 ns jitter, high speed j hs 1 1 ns dclk data rate 40 40 mhz propagation delay t phl , t plh 33 33 ns t pmclk + t pso + 3 ns pulse width distortion pwd 2 2 ns |t plh ? t phl | pulse width pw 12 12 ns within pwd limit jitter j dclk 1 1 ns v ia , v ib data rate slow dr slow 250 250 kbps within pwd limit propagation delay t phl , t plh 0.1 2.6 0.1 2.6 s 50% input to 50% output pulse width pw 4 4 s within pwd limit jitter, low speed j ls 2.5 2.5 s v ix 3 minimum input skew 4 t vix skew 10 10 ns 1 codirectional channel matching is the absolute value of the di fference in propagation delays between any two channels with inp uts on the same side of the isolation barrier. 2 the mss signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the b grade. to guar antee that mss reaches the output ahead of another fast signal, set up mss prior to the competing signal by different times depending on speed grade. 3 v ix = v ia or v ib . 4 an internal asynchronous clock not available to users samples the low speed signals. if edge sequence in codirectional channel s is critical to the end application, the leading pulse must be at least 1 t vix skew time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.
adum3150 preliminary technical data rev. pra | page 6 of 21 table 5. for all grades 1, 2, 3 parameter symbol min typ max unit test conditions/comments supply current 1 mhz, a grade and b grade i dd1 3.4 4.5 ma c l = 15 pf, dr fast = 1 mhz, dr slow = 0 mhz i dd2 5.0 6.0 ma c l = 15 pf, dr fast = 1 mhz, dr slow = 0 mhz 17 mhz, b grade i dd1 11.7 14 ma c l = 15 pf, dr fast = 17 mhz, dr slow = 0 mhz i dd2 10.0 13 ma c l = 15 pf, dr fast = 17 mhz, dr slow = 0 mhz dc specifications mckl, mss , mo, so, v ia , v ib logic high input threshold v ih 0.7v ddx v logic low input threshold v il 0.3v ddx v input hysteresis v ihyst 500 mv input current per channel i i ?1 +0.01 +1 a 0 v v input v ddx sclk, sss , mi,si, v oa , v ob , dclk logic high output voltages v oh v ddx ? 0.1 5.0 v i output = ?20 a, v input = v ih v ddx ? 0.4 4.8 v i output = ?4 ma, v input = v ih logic low output voltages v ol 0.0 0.1 v i output = 20 a, v input = v il 0.2 0.4 v i output = 4 ma, v input = v il v dd1 , v dd2 undervoltage lockout uvlo 2.6 v supply current for high speed channel dynamic input supply current i ddi(d) 0.09 ma/mbps dynamic output supply current i ddo(d) 0.02 ma/mbps supply current for all low speed channels quiescent input supply current i ddi(q) 4.5 ma quiescent output supply current i ddo(q) 5.5 ma ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common-mode transient immunity 4 |cm| 25 35 kv/s v input = v ddx , v cm = 1000 v transient magnitude = 800 v 1 v ddx = v dd1 or v dd2 . 2 v input is the input voltage of any of the mclk, mss , mo, so, v ia , or v ib pins. 3 i output is the output current of any of the sclk, dclk, sss , mi, si, v oa , or v ob pins. 4 |cm| is the maximum common-mode voltage sl ew rate that can be sustained while maintaining output voltages within the v oh and v ol limits. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
preliminary technical data adum3150 rev. pra | page 7 of 21 electrical characteristicsmixed 5 v/3.3 v operation all typical specifications are at t a = 25c and v dd1 = 5 v, v dd2 = 3.3 v. minimum and maximum specifications apply over the entire recommended operation range: 4.5 v v dd1 5.5 v, 3.0 v v dd2 3.6 v, and ?40c t a +125c, unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels, unless otherwise noted. table 6. switching specifications parameter symbol a grade b grade unit test conditions/comments min typ max min typ max mclk, mo, so spi clock rate spi mclk 40 15.6 mhz data rate fast (mo, so) dr fast 40 40 mbps within pwd limit propagation delay t phl , t plh 27 16 ns 50% input to 50% output pulse width pw 12.5 12.5 ns within pwd limit pulse width distortion pwd 3 3 ns |t plh ? t phl | codirectional channel matching 1 t pskcd 3 2 ns jitter, high speed j hs 1 1 ns mss data rate fast dr fast 40 40 mbps within pwd limit propagation delay t phl , t plh 27 26 ns 50% input to 50% output pulse width pw 12.5 12.5 ns within pwd limit pulse width distortion pwd 2 2 ns |t plh ? t phl | setup time 2 mss setup 1.5 10 ns jitter, high speed j hs 1 1 ns dclk data rate 40 40 mhz propagation delay t phl , t plh 33 33 ns t pmclk + t pso + 3 ns pulse width distortion pwd 2 2 ns |t plh ? t phl | pulse width pw 12 12 ns within pwd limit jitter j dclk 1 1 ns v ia , v ib data rate slow dr slow 250 250 kbps within pwd limit propagation delay t phl , t plh 0.1 2.6 0.1 2.6 s 50% input to 50% output pulse width pw 4 4 s within pwd limit jitter, low speed j ls 2.5 2.5 s v ix 3 minimum input skew 4 t vix skew 10 10 ns 1 codirectional channel matching is the absolute value of the di fference in propagation delays between any two channels with inp uts on the same side of the isolation barrier. 2 the mss signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the b grade. to guar antee that mss reaches the output ahead of another fast signal, set up mss prior to the competing signal by different times depending on speed grade. 3 v ix = v ia or v ib . 4 an internal asynchronous clock not available to users samples the low speed signals. if edge sequence in codirectional channel s is critical to the end application, the leading pulse must be at least 1 t vix skew time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.
adum3150 preliminary technical data rev. pra | page 8 of 21 table 7. for all grades 1, 2, 3 parameter symbol min typ max unit test conditions/comments supply current 1 mhz, a grade and b grade i dd1 4.8 6.5 ma c l = 15 pf, dr fast = 1 mhz, dr slow = 0 mhz i dd2 5.0 7.2 ma c l = 15 pf, dr fast = 1 mhz, dr slow = 0 mhz 17 mhz, b grade i dd1 14.0 17.0 ma c l = 15 pf, dr fast = 17 mhz, dr slow = 0 mhz i dd2 10.0 12.0 ma c l = 15 pf, dr fast = 17 mhz, dr slow = 0 mhz dc specifications mckl, mss , mo, so, v ia , v ib logic high input threshold v ih 0.7v ddx v logic low input threshold v il 0.3v ddx v input hysteresis v ihyst 500 mv input current per channel i i ?1 +0.01 +1 a 0 v v input v ddx sclk, sss , mi,si, v oa , v ob , dclk logic high output voltages v oh v ddx ? 0.1 5.0 v i output = ?20 a, v input = v ih v ddx ? 0.4 4.8 v i output = ?4 ma, v input = v ih logic low output voltages v ol 0.0 0.1 v i output = 20 a, v input = v il 0.2 0.4 v i output = 4 ma, v input = v il v dd1 , v dd2 undervoltage lockout uvlo 2.6 v supply current for high speed channel dynamic input supply current i ddi(d) 0.09 ma/mbps dynamic output supply current i ddo(d) 0.02 ma/mbps supply current for all low speed channels quiescent input supply current i ddi(q) 4.0 ma quiescent output supply current i ddo(q) 4.7 ma ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common-mode transient immunity 4 |cm| 25 35 kv/s v input = v ddx , v cm = 1000 v transient magnitude = 800 v 1 v ddx = v dd1 or v dd2 . 2 v input is the input voltage of any of the mclk, mss , mo, so, v ia , or v ib pins. 3 i output is the output current of any of the sclk, dclk, sss , mi, si, v oa , or v ob pins. 4 |cm| is the maximum common-mode voltage sl ew rate that can be sustained while maintaining output voltages within the v oh and v ol limits. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
preliminary technical data adum3150 rev. pra | page 9 of 21 electrical characteristicsmixed 3.3 v/5 v operation all typical specifications are at t a = 25c, v dd1 = 3.3 v and v dd2 = 5 v. minimum and maximum specifications apply over the entire recommended operation range: 3.0 v v dd1 3.6 v, 4.5 v v dd2 5.5 v, and ?40c t a +125c, unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels, unless otherwise noted. table 8. switching specifications parameter symbol a grade b grade unit test conditions/comments min typ max min typ max mclk, mo, so spi clock rate spi mclk 40 15.6 mhz data rate fast (mo, so) dr fast 40 40 mbps within pwd limit propagation delay t phl , t plh 27 16 ns 50% input to 50% output pulse width pw 12.5 12.5 ns within pwd limit pulse width distortion pwd 3 3 ns |t plh ? t phl | codirectional channel matching 1 t pskcd 5 2 ns jitter, high speed j hs 1 1 ns mss data rate fast dr fast 40 40 mbps within pwd limit propagation delay t phl , t plh 27 27 ns 50% input to 50% output pulse width pw 12.5 12.5 ns within pwd limit pulse width distortion pwd 2 3 ns |t plh ? t phl | setup time 2 mss setup 1.5 10 ns jitter, high speed j hs 1 1 ns dclk data rate 40 40 mhz propagation delay t phl , t plh 33 33 ns t pmclk + t pso + 3 ns pulse width distortion pwd 2 2 ns |t plh ? t phl | pulse width pw 12 12 ns within pwd limit jitter j dclk 1 1 ns v ia , v ib data rate slow dr slow 250 250 kbps within pwd limit propagation delay t phl , t plh 0.1 2.6 0.1 2.6 s 50% input to 50% output pulse width pw 4 4 s within pwd limit jitter, low speed j ls 2.5 2.5 s v ix 3 minimum input skew 4 t vix skew 10 10 ns 1 codirectional channel matching is the absolute value of the di fference in propagation delays between any two channels with inp uts on the same side of the isolation barrier. 2 the mss signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the b grade. to guar antee that mss reaches the output ahead of another fast signal, set up mss prior to the competing signal by different times depending on speed grade. 3 v ix = v ia or v ib . 4 an internal asynchronous clock not available to users samples the low speed signals. if edge sequence in codirectional channel s is critical to the end application, the leading pulse must be at least 1 t vix skew time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.
adum3150 preliminary technical data rev. pra | page 10 of 21 table 9. for all grades 1, 2, 3 parameter symbol min typ max unit test conditions/comments supply current 1 mhz, a grade and b grade i dd1 3.5 4.5 ma c l = 15 pf, dr fast = 1 mhz, dr slow = 0 mhz i dd2 6.5 10 ma c l = 15 pf, dr fast = 1 mhz, dr slow = 0 mhz 17 mhz, b grade i dd1 11.7 14.0 ma c l = 15 pf, dr fast = 17 mhz, dr slow = 0 mhz i dd2 13.4 17.0 ma c l = 15 pf, dr fast = 17 mhz, dr slow = 0 mhz dc specifications mckl, mss , mo, so, v ia , v ib logic high input threshold v ih 0.7v ddx v logic low input threshold v il 0.3v ddx v input hysteresis v ihyst 500 mv input current per channel i i ?1 +0.01 +1 a 0 v v input v ddx sclk, sss , mi,si, v oa , v ob , dclk logic high output voltages v oh v ddx ? 0.1 5.0 v i output = ?20 a, v input = v ih v ddx ? 0.4 4.8 v i output = ?4 ma, v input = v ih logic low output voltages v ol 0.0 0.1 v i output = 20 a, v input = v il 0.2 0.4 v i output = 4 ma, v input = v il v dd1 , v dd2 undervoltage lockout uvlo 2.6 v supply current for high speed channel dynamic input supply current i ddi(d) 0.09 ma/mbps dynamic output supply current i ddo(d) 0.02 ma/mbps supply current for all low speed channels quiescent input supply current i ddi(q) 2.8 ma quiescent output supply current i ddo(q) 6.4 ma ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common-mode transient immunity 4 |cm| 25 35 kv/s v input = v ddx , v cm = 1000 v transient magnitude = 800 v 1 v ddx = v dd1 or v dd2 . 2 v input is the input voltage of any of the mclk, mss , mo, so, v ia , or v ib pins. 3 i output is the output current of any of the sclk, dclk, sss , mi, si, v oa , or v ob pins. 4 |cm| is the maximum common-mode voltage sl ew rate that can be sustained while maintaining output voltages within the v oh and v ol limits. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
preliminary technical data adum3150 rev. pra | page 11 of 21 package characteristics table 10. parameter symbol min typ max unit test conditions/comments resistance (input-to-output) 1 r i-o 10 12 capacitance (input-to-output) 1 c i-o 1.0 pf f = 1 mhz input capacitance 2 c i 4.0 pf ic junction-to-case thermal resistance jc 75 c/w thermocouple located at center of package underside 1 the device is considered a 2-terminal device: pin 1 through pin 8 are shorted together, and pin 9 through pin 16 are shorted t ogether. 2 input capacitance is from any input data pin to ground. regulatory information the adum3150 is pending approval by the organizations listed in table 11. see table 16 and the insulation lifetime section for recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. table 11. ul (pending) csa (pending) vde (pending) recognized under 1577 component recognition program 1 approved under csa component acceptance notice 5a certified according to din v vde v 0884-10 (vde v 0884-10):2006-12 2 3750 v rms single protection basic insulation per csa 60950-1-07 and iec 60950-1 second edition, 510 v rms (721 v peak) maximum working voltage 3 reinforced insulation, 560 v peak file e214100 file 205078 file 2471900-4880-0001 1 in accordance with ul 1577, the adum3150 is proof tested by applying an insulation test voltage 1200 v rms for 1 second (current le akage detection limit = 5 a). 2 in accordance with din v vde v 0884-10, the adum3150 is proof tested by applying an insulation test voltage 525 v peak for 1 second (partial discharge detection limit = 5 pc). the asterisk (*) marked on the component designates din v vde v 0884-10 approval. 3 see table 16 for recommended maximum working vo ltages under various operating conditions. insulation and safety-related specifications table 12. parameter symbol value unit conditions rated dielectric insulation voltage 3750 v rms 1-minute duration minimum external air gap (clearance) l(i01) 5.1 mm min measured from input termin als to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 5.1 mm min measured from input termin als to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.017 mm min insulation distance through insulation tracking resistance (comparative tracking index) cti >400 v din iec 112/vde 0303 part 1 material group ii material group (din vde 0110, 1/89, table 1)
adum3150 preliminary technical data rev. pra | page 12 of 21 din v vde v 0884-10 (vde v 0884-10):2006- 12 insulation characteristics this isolator is suitable for reinforced electrical isolation only within the safety limit data. maintenance of the safety data is ensured by protective circuits. the asterisk (*) marked on packages denotes din v vde v 0884-10 approval. table 13. description test conditions/comments symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii climatic classification 40/105/21 pollution degree per din vde 0110, table 1 2 maximum working insulation voltage v iorm 560 v peak input-to-output test voltage, method b1 v iorm 1.875 = v pd(m) , 100% production test, t ini = t m = 1 sec, partial discharge < 5 pc v pd(m) 1050 v peak input-to-output test voltage, method a after environmental tests subgroup 1 v iorm 1.5 = v pd(m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc v pd(m) 840 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pd(m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc v pd(m) 672 v peak highest allowable overvoltage v iotm 5300 v peak surge isolation voltage v iosm(test) = 10 kv, 1.2 s rise time, 50 s, 50% fall time v iosm 6000 v peak safety limiting values maximum value allowed in the event of a failure (see figure 2) case temperature t s 130 c safety total dissipated power i s1 1.4 w insulation resistance at t s v io = 500 v r s >10 9 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 204060 100 80 140 120 12367-002 safe limiting power (w) ambient temperature (c) figure 2. thermal derating curve, dependence of safety limiting values with case temperature per din v vde v 0884-10 recommended operat ing conditions table 14. parameter symbol min max unit operating temperature range t a ?40 +125 c supply voltage range 1 v dd1 , v dd2 3.0 5.5 v input signal rise/fall times 1.0 ms 1 see the dc correctness and magnetic field immunity section for information on the immunity to exte rnal magnetic fields.
preliminary technical data adum3150 rev. pra | page 13 of 21 absolute maximum ratings t a = 25c, unless otherwise noted. table 15. parameter rating storage temperature (t st ) range ?65c to +150c ambient operating temperature (t a ) range ?40c to +125c supply voltages (v dd1 , v dd2 ) ?0.5 v to +7.0 v input voltages (v ia , v ib , mclk, mo, mss ) ?0.5 v to v ddi + 0.5 v output voltages (v oa , v ob ) ?0.5 v to v dd2 + 0.5 v average output current per pin 1 ?10 ma to +10 ma common-mode transients 2 ?100 kv/s to +100 kv/s 1 see figure 2 for maximum safety rated current values across temperature. 2 refers to common-mode transients across the insulation barrier. common- mode transients exceeding the ab solute maximum ratings may cause latch-up or permanent damage. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. table 16. maximum continuous working voltage 1 parameter max unit constraint ac 60 hz rms voltage 400 v rms 20 year lifetime at 0.1% failure rate, zero average voltage dc voltage 722 v peak limited by the creepage of the package, pollution degree 2, material group ii 2, 3 1 see the insulation lifetime section for more details. 2 other pollution degree an d material group requirem ents yield a different limit. 3 some system level standards allow components to use of the printed wiring board (pwb) creepage values. the supported dc voltage may be higher for those standards. esd caution
adum3150 preliminary technical data rev. pra | page 14 of 21 pin configuration and fu nction descriptions v dd1 1 gnd 1 2 mclk 3 mo 4 20 19 18 17 mi 5 mss 6 v ia 7 16 15 14 v ob 8 13 dclk 9 12 gnd 1 v dd2 gnd 2 sclk si so sss v oa v ib nic gnd 2 10 11 nic = no internal connection 12367-003 adum3150 (not to scale) top view figure 3. pin configuration table 17. pin function descriptions pin no. mnemonic direction description 1 v dd1 power input power supply for side 1. a bypass capacitor to local ground is required. 2,10 gnd 1 return ground 1. ground reference for isolator side 1. 3 mclk clock spi clock from the master controller. 4 mo input spi data from the master mo/si line. 5 mi output spi data from slave to the master mi/so line. 6 mss input slave select from the master. this signal uses an active low logic. slave select requires 10 ns setup time from the next clock or data edge. 7 v ia input low speed data input a. 8 v ob output low speed data output b. 9 dclk output delayed clock output. this pin provides a delayed copy of the mclk. 11,19 gnd 2 return ground 2. ground reference for isolator side 2. 12 nic none no internal connection. this pin is not inte rnally connected and serves no function in the adum3150. 13 v ib input low speed data input b. 14 v oa output low speed data output a. 15 sss output slave select to the slave. this signal uses an active low logic. 16 so input spi data from the slave to the master mi/so line. 17 si output spi data from the master to the slave mo/si line. 18 sclk output spi clock from the master controller. 20 v dd2 power input power supply for side 2. a bypass capacitor to local ground is required. table 18. adum3150 power off default state truth table (positive logic) 1 v dd1 state v dd2 state side 1 outputs side 2 outputs sss notes unpowered powered z z z outputs on an unpowered side are high impedance within one diode drop of ground powered unpowered z z z outputs on an unpowered side are high impedance within one diode drop of ground 1 z is high impedance.
preliminary technical data adum3150 rev. pra | page 15 of 21 typical performance characteristics 0 1 2 3 4 5 6 0 20406080 dynamic supply curren t per input channel (ma) data rate (mbps) 3.3v 5.0v 12367-004 figure 4. typical dynamic supply curren t per input channel vs. data rate for 5 v and 3.3 v operation 0 1 2 3 4 5 6 0 20406080 dynamic supply current per output channel (ma) data rate (mbps) 3.3v 5.0v 12367-005 figure 5. typical dynamic supply curren t per output channel vs. data rate for 5 v and 3.3 v operation 0 5 10 15 20 25 30 0 20406080 i dd1 supply current (ma) data rate (mbps) 3.3v 5.0v 12367-006 figure 6. typical i dd1 supply current vs. data rate for 5 v and 3.3 v operation 0 5 10 15 20 25 30 0 20406080 i dd2 supply current (ma) data rate (mbps) 3.3v 5.0v 12367-007 figure 7. typical i dd2 supply current vs. data rate for 5 v and 3.3 v operation 0 2 4 6 8 10 12 14 16 ?40 10 60 110 pr o pag a tion del a y (ns) ambient temperature (c) 3.3v 5.0v 12367-008 figure 8. typical propagation delay vs. ambient temperature for high speed channels without glitch filter (see the high speed channels section for additional information) ?40 10 60 110 ambient temperature (c) 3.3v 5.0v 0 5 10 15 20 25 pr o pag a tion del a y (ns) 12367-009 figure 9. typical propagation delay vs. ambient temperature for high speed channels with glitch filter (see the high speed channels section for additional information)
adum3150 preliminary technical data rev. pra | page 16 of 21 applications information introduction the adum3150 is part of a family of devices created to optimize isolation of spi for speed and provide additional low speed channels for control and status monitoring functions. the isolators are based on differential signaling i coupler? technology for enhanced speed and noise immunity. high speed channels the adum3150 has four high speed channels. the first three, clk, mi/so, and mo/si (the slash indicates the connection of the particular input and output channel across the isolator), are optimized for either low propagation delay in the b grade, or high noise immunity in the a grade. the difference between the grades is the addition of a glitch filter to these three channels in the a grade version, which increases propagation delay. the b grade version, with a maximum propagation delay of 14 ns, supports a maximum clock rate of 17 mhz in a standard 4-wire spi. however, because the glitch filter is not present in the b grade version, take care to make sure that spurious glitches of less than 10 ns are not present. glitches of less than 10 ns in the b grade devices can cause the second edge of the glitch to be missed. this pulse condition is seen as a spurious data transition on the output that is corrected by a refresh or the next valid data edge. it is recommended to use a grade devices in noisy environments. the relationship between the spi signal paths and the pin mnemonics of the adum3150 and data directions is summarized in table 19. table 19. pin mnemonic correspondence to spi signal path names spi signal path master side 1 data direction slave side 2 clk mclk sclk mo/si mo si mi/so mi so ss mss sss the datapaths are spi mode agnostic. the clk and mo/si channels are optimized for propagation delay and channel to channel matching. the device does not synchronize to the clock channel so there are no constraints on clock polarity or timing with respect to the data line. the ss (slave select bar) is typically an active low signal. it can have many different functions in spi and spi like busses. many of these functions are edge triggered; therefore the ss path contains a glitch filter in both a grade and b grade. the glitch filter prevents short pulses from propagating to the output or causing other errors in operation. the mss signal requires a 10 ns setup time in the b grade devices prior to the first active clock edge to allow for the added propagation time of the glitch filter. low speed data channels the low speed data channels are provided as economical isolated datapaths where timing is not critical. the dc value of all high and low speed inputs on a given side of the device is sampled simultaneously, packetized, and shifted across an isolation coil. the high speed channels are compared for dc accuracy, and the low speed data is transferred to the appropriate low speed outputs. the process is then reversed by reading the inputs on the opposite side of the device, packetizing them, and sending them back for similar processing. the dc correctness data for the high speed channels is handled internally, and the low speed data is clocked to the outputs simultaneously. this bidirectional data shuttling is regulated by a free running internal clock. because data is sampled at discrete times based on this clock, the propagation delay for a low speed channel is between 400 ns and 1.7 s depending on where the input data edge changes with respect to the internal sample clock. figure 10 illustrates the behavior of the low speed channels. ? point a: the data may change as much as 1.3 s before it is sampled, then it takes about 400 ns to propagate to the output. this appears as 1.3 s of uncertainty in the propagation delay time. ? point b: data pulses that are less than the minimum low speed pulse width may not be transmitted at all because they may not be sampled. input a output a sample cloc k output clock a b a b 12367-010 figure 10. low speed channel timing
preliminary technical data adum3150 rev. pra | page 17 of 21 delay clock the dclk function is provided to allow spi data transfers at speeds beyond the limitations usually set by propagation delay. the maximum speed of the clock in a 4-wire spi application is set by the requirement that data shifts out on one clock edge and returning data shifts in on the complementary clock edge. in isolated systems, the delay through the isolator is significant. the first clock edge, telling the slave to present its data, must propagate through the isolator. the slave acts upon it and data propagates back through the isolator to the master. the data must arrive back at the master before the complementary clock edge so that the data is shifted into the master properly. for the example shown in figure 11, if an isolator had a 50 ns propagation delay, it would require more than 100 ns for the response from the slave to arrive back at the master. this means that the fastest clock period for the spi bus is 200 ns or 5 mhz, and assumes ideal conditions, such as no trace propagation delay or delay in the slave for simplicity. master iso l a tor sl a v e clk mosi miso 12367-011 figure 11. standard spi configuration to avoid this limitation on the spi clock, a second receive buffer can be used as shown in figure 12, along with a clock signal that is delayed to match the data coming back from the slave. the proper delay of the clock was accomplished in the past by sending a copy of the clock back through a matching isolator channel and using the delayed clock to shift the slave data into a secondary buffer. using an extra channel is costly because it consumes an additional high speed isolator channel. master iso l a tor sl a v e clk mosi miso dclk 12367-012 figure 12. high speed spi using isolation channel delay the adum3150 eliminates the need for the extra high speed channel by implementing a delay circuit on the master side, as shown in figure 13. dclk is trimmed at the production test to match the round trip propagation delay of each isolator. the dclk signal can be used as if the clock signal had propagated alongside the data from the slave in the scheme outlined previously. master adum3150 slave clk mosi miso dclk delay 12367-013 figure 13. high speed spi using precision clock delay this configuration can operate at clock rates up to 40 mhz. the mi/so data is shifted into the secondary receive buffer by dclk and then transferred internally by the master to its final destination. the adum3150 does not need to use an extra expensive isolator channel to achieve these data transfer speeds. note that the ss channel is not shown here for clarity. printed circuit board (pcb) layout the adum3150 digital isolator requires no external interface circuitry for the logic interfaces. power supply bypassing is strongly recommended at both input and output supply pins: v dd1 and v dd2 (see figure 14). the capacitor value must be between 0.01 f and 0.1 f. the to tal lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. bypass < 2mm 12367-014 v dd1 gnd 1 mclk mo mi mss v ia v ob v dd2 gnd 2 sclk si so sss v oa v ib dclk gnd 1 nic gnd 2 adum3150 figure 14. recommended printed circuit board layout in applications involving high common-mode transients, it is important to minimize board coupling across the isolation barrier. furthermore, design the pcb layout so that any coupling that does occur equally affects all pins on a given component side. failure to ensure this may cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage.
adum3150 preliminary technical data rev. pra | page 18 of 21 propagation delay related parameters propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. the input-to- output propagation delay time for a high-to-low transition can differ from the propagation delay time of a low-to-high transition. input (v ix ) output (v ox ) t plh t phl 50% 50% 12367-015 figure 15. propagation delay parameters pulse width distortion is the maximum difference between these two propagation delay values, and an indication of how accurately the timing of the input signal is preserved. channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single adum3150 component. dc correctness and magnetic field immunity positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent via the transformer to the decoder. the decoder is bistable and is, therefore, either set or reset by the pulses indicating input logic transitions. in the absence of logic transitions at the input for more than ~1.2 s, a periodic set of refresh pulses indicative of the correct input state are sent via the low speed channel to ensure dc correctness at the output. if the low speed decoder receives no pulses for more than approximately 5 s, the input side is assumed to be unpowered or nonfunctional, in which case, the isolator output is forced to a default low state by the watchdog timer circuit. the limitation on the magnetic field immunity of the device is set by the condition in which induced voltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. the following analysis defines such conditions. the adum3150 is examined in a 3 v operating condition because it represents the most susceptible mode of operation of this product. the pulses at the transformer output have amplitudes greater than 1.5 v. the decoder has a sensing threshold of about 1.0 v, therefore establishing a 0.5 v margin in which induced voltages are tolerated. the voltage induced across the receiving coil is given by v = (? d M dt )? r n 2 ; n = 1, 2, , n where: is the magnetic flux density. r n is the radius of the n th turn in the receiving coil. n is the number of turns in the receiving coil. given the geometry of the receiving coil in the adum3150 and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated as shown in figure 16. magnetic field frequency (hz) maximum allowable magnetic flux density (kgauss) 1k 0.001 100 100m 10 1 0.1 0.01 10k 100k 1m 10m 12367-016 figure 16. maximum allowable external magnetic flux density for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.5 kgauss induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and does not cause a faulty output transition. if such an event occurs, with the worst-case polarity, during a transmitted pulse, it would reduce the received pulse from >1.0 v to 0.75 v. this is still well above the 0.5 v sensing threshold of the decoder. the preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the adum3150 transformers. figure 17 expresses these allowable current magni- tudes as a function of frequency for selected distances. the adum3150 is very insensitive to external fields. only extremely large, high frequency currents very close to the component may potentially be concerns. for the 1 mhz example noted, placing a 1.2 ka current 5 mm away from the adum3150 affects component operation. magnetic field frequency (hz) maximum allowable current (ka) 1000 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 12367-017 figure 17. maximum allowable current for various current to adum3150 spacings
preliminary technical data adum3150 rev. pra | page 19 of 21 note that at combinations of strong magnetic field and high frequency, any loops formed by pcb traces may induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. take care to avoid pcb structures that form loops. power consumption the supply current at a given channel of the adum3150 isolator is a function of the supply voltage, the data rate of the channel, and the output load of the channel and whether it is a high or low speed channel. the low speed channels draw a constant quiescent current due to the internal ping-pong datapath. the operating frequency is low enough that the capacitive losses due to the recommended capacitive load is negligible compared to the quiescent current. the explicit calculation for the data rate is eliminated for simplicity, and the quiescent current for each side of the isolator due to the low speed channels can be found in table 3, table 5, table 7, and table 9 for the particular operating voltages. add these quiescent currents to the high speed current calculated in the following equations for the total current for each side of the isolator. for each high speed input channel, the supply current is given by i ddi = i ddi(d) f + i ddi ( q ) for each high speed output channel, the supply current is given by i ddo = ( i ddo ( d ) + (0.5 10 ?3 ) c l v ddo ) f + i ddo ( q ) where: i ddi (d) , i ddo (d) are the input and output dynamic supply currents per channel (ma/mbps). c l is the output load capacitance (pf). v ddo is the output supply voltage (v). f is the input logic signal data rate, expressed in units of mbps. i ddi(q) , i ddo(q) are the specified input and output quiescent supply currents (ma). to calculate the total v dd1 and v dd2 supply current, the supply currents for each input and output channel corresponding to v dd1 and v dd2 are calculated and totaled. figure 4 and figure 5 show per channel supply currents as a function of data rate for an unloaded output condition. figure 6 and figure 7 show the total v dd1 and v dd2 supply current as a function of data rate for adum3150 channel configurations with all high speed channels running at the same data rate and the low speed channels at idle. insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation as well as on the materials and material interfaces. there are two types of insulation degradation of primary interest: breakdown along surfaces exposed to the air and insulation wear out. surface breakdown is the phenomenon of surface tracking and the primary determinant of surface creepage requirements in system level standards. insulation wear out is the phenomenon where charge injection or displacement currents inside the insulation material cause long-term insulation degradation. surface tracking surface tracking is addressed in electrical safety standards by setting a minimum surface creepage based on the working voltage, the environmental conditions, and the properties of the insulation material. safety agencies perform characterization testing on the surface insulation of components that allows the components to be categorized in different material groups. lower material group ratings are more resistant to surface tracking and therefore can provide adequate lifetime with smaller creepage. the minimum creepage for a given working voltage and material group is in each system level standard and is based on the total rms voltage across the isolation, pollution degree, and material group. the material group and creepage for the adum3150 isolator is presented in table 12. insulation wear out the lifetime of insulation due to wear out is determined by its thickness, material properties, and the voltage stress applied. it is important to verify that the product lifetime is adequate at the application working voltage. the working voltage supported by an isolator for wear out may not be the same as the working voltage supported for tracking. it is the working voltage applicable to tracking that is specified in most standards. testing and modeling have shown that the primary driver of long- term degradation is displacement current in the polyimide insulation causing incremental damage. the stress on the insulation can be broken down into broad categories, such as: dc stress, which causes very little wear out because there is no displacement current, and an ac component time varying voltage stress, which causes wear out. the ratings in certification documents are usually based on 60 hz sinusoidal stress because this reflects isolation from line voltage. however, many practical applications have combinations of 60 hz ac and dc across the barrier as shown in equation 1. because only the ac portion of the stress causes wear out, the equation can be rearranged to solve for the ac rms voltage, as is shown in equation 2. for insulation wear out with the polyimide materials used in this product, the ac rms voltage determines the product lifetime. 2 2 dc rms ac rms v v v ? ? (1) or 2 2 dc rms rms ac v v v ? ? (2) where: v ac rms is the time varying potion of the working voltage. v dc is the dc offset of the working voltage. v rms is the total rms working voltage of the working voltage.
adum3150 preliminary technical data rev. pra | page 20 of 21 calculation and use of parameters example the following is an example that frequently arises in power conversion applications. assume that the line voltage on one side of the isolation is 240 v ac rms and a 400 v dc bus voltage is present on the other side of the isolation barrier. the isolator material is polyimide. to establish the critical voltages in determining the creepage clearance and lifetime of a device, see figure 18 and the following equations. iso l a tion v o ltage time v ac rms v rms v dc 12367-018 v peak figure 18. critical voltage example the working voltage across the barrier from equation 1 is 2 2 dc rms ac rms v v v ? ? 2 2 400 240 ? ? rms v v rms = 466 v this is the working voltage used along with the material group and pollution degree when looking up the creepage required by a system standard. to determine if the lifetime is adequate, obtain the time varying portion of the working voltage. the ac rms voltage can be obtained from equation 2. 2 2 dc rms rms ac v v v ? ? 2 2 400 466 ? ? rms ac v v ac rms = 24 v rms in this case, ac rms voltage is simply the line voltage of 240 v rms. this calculation is more relevant when the waveform is not sinusoidal. the value is compared to the limits for working voltage in table 16 for expected lifetime, under a 60 hz sine wave, and it is well within the limit for a 50 year service life. note that the dc working voltage limit in table 16 is set by the creepage of the package as specified in iec 60664-1. this value may differ for specific system level standards.
preliminary technical data adum3150 rev. pra | page 21 of 21 outline dimensions compliant to jedec standards mo-150-ae 060106-a 20 11 10 1 7.50 7.20 6.90 8.20 7.80 7.40 5.60 5.30 5.00 seating plane 0.05 min 0.65 bsc 2.00 max 0.38 0.22 coplanarity 0.10 1.85 1.75 1.65 0.25 0.09 0.95 0.75 0.55 8 4 0 figure 19. 20-lead shrink small outline package [ssop] (rs-20) dimensions shown in millimeters ordering guide model 1 no. of inputs, v dd1 side no. of inputs, v dd2 side maximum data rate (mhz) maximum propagation delay, 5 v (ns) isolation rating (v ac) temperature range package description package option adum3150arsz 4 2 40 25 3750 ?40c to +125c 20-lead ssop rs-20 ADUM3150ARSZ-RL7 4 2 40 25 3750 ?40c to +125c 20-lead ssop, 7 reel rs-20 adum3150brsz 4 2 40 14 3750 ?40c to +125c 20-lead ssop rs-20 adum3150brsz-rl7 4 2 40 14 3750 ?40c to +125c 20-lead ssop, 7 reel rs-20 eval-adum3154z evaluation board 1 z = rohs compliant part. ?2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr12367-0-6/14(pra)

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